The present invention relates to a semiconductor device and more particularly a semiconductor device being capable of operating at a high speed.
It is essential for the improvement of performance of computer systems to operate memory devices at a high speed by shortening the access time.
In semiconductor memory devices, time delay of a select or deselect signal derived from a decoder and propagated on a word line (to be referred to as "the word line time delay" in this specification) is dependent upon the material of a word line and the size of a transistor which constitutes a transfer gate. That is, a signal propagation time is dependent upon the resistance of a word line and the capacitance produced because the word line is connected to a plurality of transfer gates for memory cells or the capacitance produced because the word line functions as a plurality of transfer gates for memory cells. Therefore, a time period from the time when an output from a decoder appears at its output terminal to the time when the output reaches the transfer gate farthest from the decoder; that is, the word line time delay td is given by EQU td.perspectiveto.CR (1)
where R is the resistance from one end of a word line; that is, the output of a decoder to the other or terminal end of the word line; and C is the capacitance of the word line.
Meanwhile semiconductor devices with more elements are fabricated in order to increase the memory capacity. As the number of memory cells is increased, the capacitance C is also increased and the word lines are increased in length so that the resistance R is also increased. Therefore, as is clear from Eq. (1), it is readily understood that in the high-density memory cells the word line time delay td is remarkably increased. Such long word line time delay td in memory devices prevents the high speed operation of the computer systems.
Therefore, there have been devised and demonstrated various methods and devices for shortening the word line time delay td, but none of them is satisfactory in practice. That is, the switching the memory cell from selection mode to deselection mode is slow so that information is erroneously stored in the deselected memory cell.